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MP1493 3a, 4.2v-16v input, fast transient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 1 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the MP1493 is a fully integrated, high? efficiency 3a synchronous rectified step-down converter. the MP1493 operates at high efficiency over a wide output current load range. adaptive constant-on-time (cot) control mode provides fast transient response, eases loop stabilization, and operates with a low-cost electrolytic capacitor. the MP1493 requires a minimum number of readily available standard external components and is available in an 8-pin soic rohs compliant package. features ? wide 4.2v to 16v operating input range ? 3a output current ? adaptive cot for fast transient response ? low r ds (on) internal power mosfets ? proprietary switching loss reduction technique ? programmable switching frequency ? ocp, scp, ovp, uvp protection and thermal shutdown ? optional ocp protection: latch-off mode and hiccup mode ? output adjustable from 0.805v to 13v applications ? digital set top boxes ? flat panel television and monitors ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithi c power systems, inc. typical application 6 7 8 2 3 1 4 r 7 453k 499k MP1493 vin on/off 5 vout 2.5v r1 41k r2 20k in freq byp en gnd fb sw bst
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 2 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number ocp protection package top marking free air temperature (t a ) MP1493ds* latch-off mode MP1493 MP1493ds-a hiccup mode soic8 MP1493-a -40 c to +85 c * for tape & reel, add suffix ?z (e.g. MP1493ds?z). for rohs compliant packaging, add suffix ?lf (e.g. MP1493ds?lf?z) package reference soic8 absolute maxi mum ratings (1) supply voltage v in ....................................... 19v v sw ...................................................................... -0.3v (-5v for <10ns) to 19v (24v for <10ns) v bst ...................................................... v sw + 6v all other pins ..................................-0.3v to +6v continuous power dissipation (t a = +25c) (2) soic8 ...................................................... 1.39w junction temperature ..............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (3) supply voltage v in ...........................4.2v to 16v output voltage v out .....................0.805v to 13v operating junction temp. (t j ). -40c to +125c thermal resistance (4) ja jc soic8..................................... 90 ...... 45... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 3 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t a = +25 c, unless otherwise noted. parameters symbol condition min typ max units supply current (shutdown) i in v en =0v 5 a supply current (quiescent, not switching) i in v en =2v, v fb =0.9v 1 ma hs switch on resistance hs rds-on 120 m ? ls switch on resistance ls rds-on 60 m ? switch leakage sw lkg v en =0v, v sw =0v or 12v 0 10 a current limit (5) i limit after soft-start time-out 4.0 5.0 a one-shot on time t on r 7 =300k ? ,v out =1.2v 250 ns minimum off time t off 130 150 ns fold-back off time t fb i lim =1 1.25 s ocp hold-off time t oc i lim =1 50 s feedback voltage v fb 789 805 821 mv feedback current i fb v fb =800mv 10 50 na soft start time t ss 1 ms en rising threshold vilen 1.05 1.35 1.6 v en threshold hysteresis vihen 500 mv v en =2v 2 en input current i en v en =0v 0 a vin under voltage lockout threshold rising inuvvth 3.1 v vin under voltage lockout threshold hysteresis inuvhys 300 mv thermal shutdown 150 c thermal shutdown hysteresis 25 c note: 5) guaranteed by design and characterization..
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 4 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions soic-8 pin # name description 1 in supply voltage. the MP1493 operates from a +4.2v to +16v input rail. c1 is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 2 gnd system ground. this pin is the reference gr ound of the regulated output voltage. for this reason care must be taken in pcb layout. 3 sw switch output. use wide pcb traces and multiple vias to make the connection. 4 bst bootstrap. a capacitor connected between sw and bst pins is required to form a floating supply across the high-side switch driver. 5 byp internal ldo output. decouple with a 1f cera mic capacitor. x7r or x5r grade dielectric ceramic capacitors are recommended for t heir stable temperature characteristics. 6 en en=1 to enable the MP1493. for automatic start-up, connect en pin to vin with a pull-up resistor. 7 fb feedback. an external resistor divider from t he output to gnd, tapped to the fb pin, sets the output voltage. 8 freq switching frequency setting pin during ccm operation. connect a resistor r 7 to in to set the switching frequency. an optional 1nf decoup ling capacitor can be added to improve any switching frequency jitter that may be present.
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 5 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in =12v, v out =1.2v, l=2.2h, t a =+25c, unless otherwise noted. line regulation load regulation frequency vs. temperature i out (a) i out (a) i out (a) 60 65 70 75 80 85 90 95 100 0.01 0.1 1 10 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 3 5 7 9 11 13 15 16 v in (v) -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 400 405 410 415 420 425 430 435 440 445 450 -40 -20 0 20 40 60 80 100 120140 f sw (khz) v in =8v v in =12v i out =3a v in =12v no air flow v out vs. i out v out =1.2v, freq=500khz i out (a) v out (v) 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 0.01 0.1 1 10 v in =16v v in =12v v in =5v v in =8v
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 6 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.2v, l=2.2h, t a =+25c, unless otherwise noted.
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 7 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1.2v, l=2.2h, t a =+25c, unless otherwise noted.
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 8 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram figure 1?function block diagram
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 9 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation pwm operation the MP1493 is a fully integrated synchronous rectified step-down switch converter. adaptive constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (fb) is below the reference voltage (ref) which indicates insufficient output voltage. the on period is determined by the input voltage and the frequency-set resistor as follows: =+ ? freq on in 9.3 r (k ) t(ns) 40ns v(v) 0.4 (1) after the on period elapses, the hs-fet is turned off. it is turned on again when fb drops below ref. by repeating operation in this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs- fet and ls-fet are turned on at the same time. it?s called shoot-through. in order to avoid shoot- through, a dead-time (dt) is internally generated between hs-fet off and ls-fet on. when the output current is high, the hs-fet and ls-fet repeat on/off as described above. in this operation, the inductor current will never go to zero. it?s called continuous-conduction-mode (ccm) operation. in ccm operation, the switching frequency (fs) is fairly constant. light-load operation when the load current decreases, MP1493 reduces the switching frequency automatically to maintain high efficiency. as the output current reduces from heavy-load condition, the inductor current decreases as well, and eventually comes close to zero current. the ls-fet driver turns into tri-state (high z) whenever the inductor current reaches zero level. the current modulator takes over the control of ls-fet and limits the inductor current to less than -1ma. hence, efficiency at light-load condition is optimized. figure 2 floating driver and bootstrap charging the floating power mosfet driver is powered by an external bootstrap capacitor. this floating driver has its own uvlo protection. this uvlo?s rising threshold is 2.2v with a hysteresis of 150mv. the bootstrap capacitor voltage is charged from vcc through n1 (figure 3). n1 turns on when ls switches turns on and turns off when ls switch turns off. switching frequency adaptive constant-on-time (cot) control is used in MP1493 and there is no dedicated oscillator in the ic. the input voltage is feed-forwarded to the on-time one-shot timer through the resistor r 7 . the duty ratio is kept as v out /v in . hence the switching frequency is fairly constant over the input voltage range. the switching frequency can be set as follows: = + ? 6 s 7in delay in out 10 f(khz) 9.3 r (k ) v (v) t(ns) v(v) 0.4 v (v) (2) where tdelay is the comparator delay, it?s about 40ns. MP1493 is optimized to operate at high switching frequency but with high efficiency. high switching frequency makes it possible to utilize small sized lc filter components to save system pcb space. jitter and fb ramp slope figure 3 and figure 4 show jitter occurring in both pwm mode and skip mode. when there is noise in the v fb downward slope, the on time of
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 10 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. hs-fet deviates from its intended location and produces jitter. it is necessary to understand that there is a relationship between a system?s stability and the steepness of the v fb ripple?s downward slope. the slope steepness of the v fb ripple dominates in noise immunity. the magnitude of the v fb ripple doesn?t directly affect the noise immunity directly. figure 3?jitter in pwm mode figure 4?jitter in skip mode ramp with large esr cap in the case of poscap or other types of capacitor with larger esr is applied as output capacitor. the esr ripple dominates the output ripple, and the slope on the fb is quite esr related. figure 5 shows an equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. turn to application information section for design steps with large esr caps. figure 5?simplified circuit in pwm mode without external ramp compensation to realize the stability when no external ramp is used, usually the esr value should be chosen as follow: sw on esr out tt 0.7 2 r c + (3) t sw is the switching period. ramp with small esr cap when the output capacitors are ceramic ones, the esr ripple is not high enough to stabilize the system, and external ramp compensation is needed. skip to application information section for design steps with small esr caps. figure 6?simplified circuit in pwm mode with external ramp compensation in pwm mode, an equivalent circuit with hs-fet off and the use of an external ramp compensation circuit (r4, c4) is simplified in figure 6. the external ramp is derived from the inductor ripple current. if one chooses c4, r9, r1 and r2 to meet the following condition: 12 9 sw 4 1 2 rr 11 r 2f c 5rr ?? < + ?? + ?? (4) where: r4 c4 fb c4 iiii = + (5) and the ramp on the v fb can then be estimated as: in out 12 ramp on 44 12 9 vv r//r vt rc r//rr ? = + (6) the downward slope of the v fb ripple then follows ? ? == out ramp slope1 off 4 4 v v v trc (7)
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 11 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. as can be seen from equation 7, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 4, then we can only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 8. sw on -3 esr out slope1 out out sw on tt +-rc io 10 0.7 2 -v v + 2lc t -t (8) io is the load current. in skip mode, the downward slope of the v fb ripple is almost the same whether the external ramp is used or not. figure 7 shows the simplified circuit of the skip mode when both the hs-fet and ls-fet are off. figure 7?simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follow: () ref slope2 12 out v v (r r //ro) c ? = + (9) where ro is the equivalent load resistor. as described in figure 4, v slope2 in the skip mode is lower than that is in the pwm mode, so it is reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during ultra light load condition, the values of the v fb resistors should not be too big, however, that will decrease the ultra light load efficiency. soft start/stop MP1493 employs soft start/stop (ss) mechanism to ensure smooth output du ring power up and power shut-down. when the en pin becomes high, an internal ss voltage ramps up slowly. the ss voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once ss voltage reaches the same level of the ref voltage, it keeps ramping up, while ref takes over the pwm comparator. at this point, the soft start finishes, it enters steady state operation. the ss time is about 1ms. when the en pin becomes low, the internal ss voltage is discharged through an internal current source. once the ss voltage reaches ref voltage, it takes over the pwm comparator. the output voltage will decrease smoothly with ss voltage until zero level. s over-current protection (ocp) and short- circuit protection (scp) MP1493 has cycle-by cycle over-current limit control. the inductor current is monitored during the on state. and it has two optional ocp/scp protection modes: latch-off mode and hiccup mode. for MP1493ds, the hs-fet turns off when the inductor current exceeds the current limit and the ocp timer?set at 50 s?starts. the ocp triggers if the inductor current reaches or exceeds the current limit every cycle in those 50 s. the MP1493ds short-circuit protection (scp) occurs when dead shorts occur?when the inductor current exceeds the current limit and the fb voltage is lower than 50% of the v ref ?and will trigger the ocp. for MP1493ds-a, enters hiccup mode, that periodically restarts the part when the inductor current peak value exceeds the current limit and v fb drops below the under-voltage (uv) threshold. typically, the uv threshold is 50% below the ref voltage. in ocp/scp, MP1493ds-a will disable the output voltage power, discharge internal soft-start cap, and then automatically try to soft-start again. if the over-current circuit condition still holds after soft-start ends, it repeats this operation cycle until the over-current circuit condition disappears, and output rises back to regulation level. over/under-voltage protection (ovp/uvp) MP1493 monitors the output voltage through a resistor divided feedback (fb) voltage to detect over and under voltage on the output. when the fb voltage is higher than 125% of the ref voltage, it?ll trigger ovp. once it triggers ovp, the ls-fet is always on, while the hs-fet is off. it needs power cycle to power up again. when
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 12 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the fb voltage is below 50% of the ref voltage (0.805v), uvp will be triggered. usually uvp comes with current limit is hit, hence it results in scp. uvlo protection MP1493 has under-voltage lock-out protection (uvlo). when the input voltage is higher than the uvlo rising threshold voltage, the MP1493 powers up. it shuts off when the input voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. thermal shutdown thermal shutdown is employed in MP1493. the junction temperature of the ic is monitored internally. if the junction temperature exceeds the threshold value (typically 150oc), the converter shuts off. this is non-latch protection. there is about 25oc hysteresis. once the junction temperature drops around 125oc, it initiates a ss .
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 13 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information setting the output voltage-large esr caps for applications that electrolytic capacitor or pos capacitor with a controlled output of esr is set as output capacitors. the output voltage is set by feedback resistors r1 and r2. as figure 8 shows. figure 8?simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? - 50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. then r1 is determined as follow with the output ripple considered: out out ref 12 ref 1 vvv 2 rr v ? ? = (10) out v is the output ripple determined by equation 19. figure 9?simplified circuit of ceramic capacitor setting the output voltage-small esr caps when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4.the output voltage is influenced by ramp voltage v ramp besides r divider. the v ramp can be calculated as shown in equation 6, r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? - 50k ? for r2, using a comparatively larger r2 when vo is low, etc.,1.05v, and a smaller r2 when vo is high. and the value of r1 then is determined as follow: 2 1 fb(avg) 2 out fb(avg) 4 9 r r= v r - (v -v ) r +r (11) the v fb(avg) is the average value on the fb, v fb(avg) varies with the vin, vo, and load condition, etc., its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ,if one wants to gets a better load or line regulation, a lower vramp is suggested once it meets equation 8. for pwm operation, v fb(avg) value can be deduced from equation 12. 12 fb( avg) ref ramp 12 9 r//r 1 vvv 2r//rr =+ + (12) usually, r9 is set to 0 ? , and it can also be set following equation 13 for a better noise immunity. it should also set to be 5 timers smaller than r1//r2 to minimize its influence on vramp. 9 4sw 1 r 2c2f (13) using equation 11 to calculate the output voltage can be complicated. to simplify the calculation of r1 in equation 11, a dc-blocking capacitor cdc can be added to filter the dc influence from r4 and r9. figure 10 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using equation 14 for pwm mode operation. ?? = + out ref ramp 12 ref ramp 1 (v v v ) 2 rr 1 vv 2 (14) cdc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should also not larger than 0.47uf considering start up performance. in case one wants to use a
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 14 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. larger cdc for a better fb noise immunity, combined with reduced r1 and r2 to limit the cdc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load and line regulation are still vramp related. figure 10?simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance. in the layout, it?s recommended to put the input capacitor as close as possible to the vin pin. the capacitance varies significantly over temperature. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable over temperature. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: out out cin out in in vv ii (1 ) vv = ? (15) the worst-case condition occurs at v in = 2v out , where: out cin i i 2 = (16) for simplification, choose the input capacitor whose rms current rating is greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system design, choose the input capacitor that meets the specification. the input voltage ripple can be estimated as follows: out out out in sin in in iv v v(1) fc v v = ? (17) the worst-case condition occurs at vin = 2v out , where: out in sin i 1 v 4f c = (18) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc = ? + (19) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated by: out out out 2 sout in vv v(1) 8f lc v = ? (20) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equation 4, 7 and 8. in the case of poscap or electrolytic capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. so the external ramp is not recommended. a minimum esr value of 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated to: out out out esr sin vv v(1)r fl v = ? (21) maximum output capacitor limitation should be also considered in design application. MP1493 has an around 1ms soft-start time period. if the output capacitor value is too high, the output
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 15 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. voltage can?t reach the design value during the soft-start time, and then it will fail to regulate. the maximum output capacitor value c o_max can be limited approximately by: o_max lim_avg out ss out c(i i)t/v =? (22) where, i lim_avg is the average start-up current during soft-start period. t ss is the soft-start time. inductor the inductor is required to supply constant current to the output load while being driven by the switched input voltage. a larger value inductor will result in less ripple current that will result in lower output ripple voltage. however, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. a good rule of thumb for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit. also, make sure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated by: out out sl in vv l(1) fi v =? (23) where i l is the peak-to-peak inductor ripple current. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated by: out out lp out sin vv ii (1 ) 2f l v =+ ? (24) application recommendation as figure 8 shows, when output cap is electrolytic poscap, etc with large esr, no external ramp is needed. recommended parameters are listed below in table 1 to table 3 table 1?300khz recommended parameters without external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 3.3 12.1 26.1 402 2.5 3.3 30 14.3 820 3.3 3.3 40.2 13.3 1000 table 2?500khz recommended parameters without external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 3.3 12.1 26.1 240 2.5 3.3 30 14.3 510 3.3 3.3 40.2 13.3 649 table 3?700khz recommended parameters without external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1.2 2.2 12.1 26.1 174 2.5 2.2 30 14.3 348 3.3 2.2 40.2 13.3 475 when output cap is ceramic caps with lower esr, external ramp is needed as shown in fig.9. recommended parameters are as listed in table 4 to table 6 with r9=0 ? . table 4?300khz recommended parameters with external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 3.3 12.1 26.1 330 220 402 2.5 3.3 30 14.3 698 220 820 3.3 3.3 40.2 12.7 698 220 1000 table 5?500khz recommended parameters with external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 3.3 12.1 26.1 402 220 240 2.5 3.3 30 14.3 549 220 510 3.3 3.3 40.2 12.7 698 220 649
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 16 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. table 6?700khz recommended parameters with external ramp compensation recommended conditions: v in =12v, i out =3a v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1.2 2.2 12.1 26.1 330 220 174 2.5 2.2 30 14.3 549 220 348 3.3 2.2 40.2 12.7 698 220 475 according to equation (22) and some design abundance are reserved, recommended maximum output capacitor value is as below table 7 shown. table 7?recommended maximum output capacitor value (f s =500 khz) recommended conditions: v in =12v, i out =3a v out (v) 1.2 1.8 2.5 3.3 5 c o_max ( f) 680 570 390 330 220 the detailed application schematic is shown in figure 11, fig12 and figure 13. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more possible applications of this device, please refer to related evaluation board data sheets. MP1493 1 5 8 6 7 3 4 2 byp en fb sw bst gnd freq in figure 11?typical application circuit with no external ramp MP1493 1 5 8 6 7 r9 0 3 4 2 byp en fb sw bst gnd freq in figure 12?typical application circuit with low esr ceramic capacitor
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter MP1493 rev. 1.15 www.monolithicpower.com 17 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. MP1493 1 5 8 6 7 c dc 10nf 3 4 2 byp en fb sw bst gnd freq in figure 13?typtical application schematic with low esr ceramic capacitor and dc blocking capacitor . layout recommendation 1) put the input capacitors as close as possible to the in pin. 2) put the decoupling capacitor as close as possible to the v cc pin. 3) put the inductor as close as possible to sw pin. make the sw pad as large as possible to minimize the switching noise interference. 4) the fb pin is directly connected to the pwm comparator. it should be routed away from the noisy sw node.
MP1493 ? 3a, 4.2v-16v input, fast trans ient synchronous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP1493 rev. 1.15 www.monolithicpower.com 18 12/9/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation aa. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane

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